1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating an analog semiconductor device on a surface of a semiconductor substrate and in a step configuration with respect to it, that prevents unwanted residual matter from remaining in the concave corner of the step configuration after an etching process step.
2. Discussion of the Prior Art
A conventional method of fabricating an analog semiconductor device on a surface of a semiconductor substrate is described with reference to FIGS. 1 and 2A-2C.
Referring to FIG. 1, a semiconductor substrate 100 is provided with a surface. The surface has designated on it an analog portion 3, a digital portion 5, and a margin portion 7 between the analog and the digital portion. An insulating layer 2 is formed on the analog portion and at least a part of the margin portion.
Then a structure having analog properties is formed on the analog portion as follows. A first polysilicon layer 4 having a thickness of 2000 A is formed on layer 2. Then an oxide layer and a nitride layer are deposited sequentially on polysilicon layer 4, having thicknesses of 70 A and 700 A respectively. The oxide layer and the nitride layer thus form an ON (Oxide/Nitride) structure 6. Then ON structure 6 and polysilicon layer 4 are patterned through a photolithographic method into a designated pattern. The pattern from polysilicon layer 4 is a part of the analog semiconductor device, and is also known as first designated pattern. Its lateral side closest to the digital portion is at the boundary of the analog portion and the margin portion.
As seen in FIG. 1, the analog structure is thus in a step configuration 9 with respect to the top surface of the section of the insulating layer that is on the margin portion. The step configuration is formed from the top surface of structure 6, the lateral side of the first designated pattern closest to the digital portion, and the top surface of the section of the insulating layer that is on the margin portion. The step configuration thus defines a convex corner where the top surface meets the lateral side. The step configuration also defines a concave corner in the vicinity where the insulating layer meets the lateral side. The two corners have a height difference that is called a step difference of the step configuration.
A digital device is then formed on the digital portion of the substrate surface. The next process step, shown in FIG. 2A, is to form a gate oxide layer 8 of thickness 120 A by oxidation.
A second polysilicon layer 10 and a WSix layer 12 are then deposited sequentially on the entire resulting structure, each having a thickness of 1500 A. Layers 10 and 12 will be used to form gates on the analog and digital devices. A plasma enhanced ("PE")-oxide layer 14 and a SiON layer 16 are then deposited sequentially on layer 12, having thicknesses of 2000 A and 620 A respectively. Layers 14 and 16 function as an anti-reflective surface.
Then PE-oxide layer 14 is etched into a designated pattern by a photolithographic method. Next WSix layer 12 is patterned, using the PE-oxide pattern as a mask, resulting in the structure shown in FIG. 2B. Then second polysilicon layer 10 is selectively etched using the WSix pattern as a mask. This forms a second designated pattern.
WSix layer 12 and polysilicon layer 10 are etched by the oxide layer hard masking technique using oxide layer 14. This patterns normally the structure in the digital portion of the surface. However, etching is not completed in the margin portion, if the step difference is high. That is because the high step difference has caused the polysilicon and WSix layers to be relatively thick at the concave corner of the step configuration. Accordingly, residual matter from WSix layer 12 remains on layer 10 in stringer form A.
Further, as seen in FIG. 2C, when polysilicon layer 10 is removed, residual matter from it remains in the concave corner of the step configuration in stringer form B. Such residual matters affect the subsequent process steps in the fabrication method. Worse, the residual matter can bridge the analog device with the substrate, which causes leakage. The problem is exacerbated when the digital device is nearby. This causes the overall device to fail in the ESD (Electro-Static Discharge) and package tests that are performed after the fabrication method is completed, which reduces the yield of the product.
In the prior art such residual matters are removed sometimes by additional etching. This generally poses the risk of overetching, which creates the hazard of pitting.